The present disclosure relates to semiconductor devices and methods for fabricating the same, and more particularly, to a metal insulator semiconductor (MIS) device including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a method for fabricating the MIS device.
In order to meet the demands for increased speed and reduced power consumption of semiconductor integrated circuit devices, in respect of metal insulator semiconductor field-effect transistors (MISFET, hereinafter referred to as MIS transistors), progress has been made in reducing the thicknesses of gate insulating films. When silicon dioxide which has been conventionally used is formed into a thin film for the purpose of reducing the thickness of a gate insulating film, a gate leakage current caused by a tunnel current increases. Consequently, an attempt to prevent depletion of a gate electrode has been made. Specifically, the attempt has been carried out by reducing an equivalent oxide thickness (EOT) by means of use of, instead of the silicon dioxide film, a so-called high dielectric constant insulating film such as an HfO2 film as the gate insulating film, and by employing a so-called metal inserted poly silicon (MIPS) structure in which a polysilicon film serving as a gate electrode and a gate insulating film sandwich a metal-containing film as part of the gate electrode (see, for example, T. Schram, et al., Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only, Symp. On VLSI technology, 44 (2008)). Note that the high dielectric constant insulating film refers to an insulating film having a relative dielectric constant of, for example, 8 or more, which is higher than that of a silicon nitride film.
A method for fabricating a conventional semiconductor device will be described below with reference to FIGS. 11-13. This conventional semiconductor device includes a complementary metal insulator semiconductor (CMIS) device composed of an n-type MIS transistor and a p-type MIS transistor which are provided on an identical substrate. In this device, a gate insulating film is made of an HfO2 film, and a gate electrode has a MIPS structure. FIGS. 11-13 are cross-sectional views (taken along a gate length direction) illustrating sequential steps of the method for fabricating the conventional semiconductor device. In FIGS. 11-13, “nMIS transistor region” shown at the left refers to a region where the n-type MIS transistor is formed, and “pMIS transistor region” shown at the right refers to a region where the p-type MIS transistor is formed.
First, as shown in FIG. 11, a pMIS transistor region and an nMIS transistor region are defined by selectively forming a shallow trench isolation 101 in an upper portion of a semiconductor substrate 100 of p-type silicon. Here, a portion of the semiconductor substrate 100 surrounded by the shallow trench isolation 101 and located in the pMIS transistor region serves as an active region 100a, and a portion of the semiconductor substrate 100 surrounded by the shallow trench isolation 101 and located in the nMIS transistor region serves as an active region 100b. 
Next, an n-type well region 121N is formed in the pMIS transistor region of the semiconductor substrate 100, and a p-type well region 121P is formed in the nMIS transistor region of the semiconductor substrate 100. Thereafter, photolithography and dry etching are performed to form a gate electrode 123a on the active region 100a in the pMIS transistor region with a gate insulating film 122a interposed between the gate electrode 123a and the active region 100a. The photolithography and the dry etching also form a gate electrode 123b on the active region 100b in the nMIS transistor region with a gate insulating film 122b interposed between the gate electrode 123b and the active region 100b. 
The gate insulating film 122a includes an interface layer 102a made of a silicon dioxide film, a high dielectric constant insulating film (hereinafter, referred to as a high-k film) 103a formed on the interface layer 102a and made of an HfO2 film, and a pMIS cap film 104a formed on the high-k film 103a. The gate insulating film 122b includes an interface layer 102b made of a silicon dioxide film, a high-k film 103b formed on the interface layer 102b and made of an HfO2 film, and an nMIS cap film 104b formed on the high-k film 103b. The pMIS cap film 104a and the nMIS cap film 104b enable control of a work function of each of the gate electrodes 123a and 123b. 
The gate electrode 123a includes a metal film 106a and a polysilicon film 107a formed on the metal film 106a. The gate electrode 123b includes a metal film 106b and a polysilicon film 107b formed on the metal film 106b. 
Next, as shown in FIG. 12, extension regions 108a are formed at both sides of the gate electrode 123a by introducing a p-type impurity into the pMIS transistor region of the semiconductor substrate 100, and extension regions 108b are formed at both sides of the gate electrode 123b by introducing an n-type impurity into the nMIS transistor region of the semiconductor substrate 100.
After a silicon dioxide film and a silicon nitride film are sequentially deposited on the entire surface of the semiconductor substrate 100, the deposited silicon nitride film and the deposited silicon dioxide film are subjected to anisotropic etching. Consequently, as shown in FIG. 13, sidewall spacers 111a including a silicon dioxide film 109a and a silicon nitride film 110a are formed on both side surfaces of the gate electrode 123a, and sidewall spacers 111b including a silicon dioxide film 109b and a silicon nitride film 110b are formed on both side surfaces of the gate electrode 123b. Thereafter, source/drain regions 112a are formed at both sides of the gate electrode 123a sandwiched between the sidewall pacers 111a by introducing a p-type impurity into the pMIS transistor region of the semiconductor substrate 100, and source/drain regions 112b are formed at both sides of the gate electrode 123b sandwiched between the sidewall pacers 111b by introducing an n-type impurity into the nMIS transistor region of the semiconductor substrate 100. In this manner, the CMIS device is formed through the foregoing steps.